Many host systems ranging from large enterprise servers to personal computers employ a variety of memory subsystems to provide data for use with a central processing unit (CPU). Host systems often use a hierarchy of memories with different speeds and capacities. Higher capacity memories typically have longer latency and therefore are slower than lower capacity memories. In a typical memory hierarchy a CPU communicates directly with high-speed registers and a cache memory, transferring small amounts of data at a rate comparable to the CPU speed. The cache memory prefetches a larger block of data from a dynamic random access memory (DRAM), but at a rate slower than the CPU speed. The cache takes advantage of the sequential nature of many data requests by the CPU to minimize CPU stalls or situations where the CPU cannot complete a task for lack of necessary data. The DRAM also prefetches a larger block of data from a hard disk drive (HDD). At each level in the hierarchy it is important to prefetch a block of data sufficiently large to compensate for the slower prefetch rate. This permits the average data rate to be maintained at all levels of the hierarchy. HDD memories are significantly slower than DRAMs and other solid-state memories because of their mechanical nature. Preferably each level of memory hierarchy provides several orders of magnitude increase in memory capacity with a single order of magnitude increase in latency. The significant increase in latency between the DRAM and HDD memory hierarchy levels necessitates a memory solution with performance and capacity in between what is available from DRAM and HDD technologies so that data flow is balanced throughout the memory hierarchy.
Conventional memory modules communicate through a shared bus. This results in a high capacitive loading on the shared bus that reduces memory speed. The shared bus approach also creates stubs when memory modules are removed. Stubs are conduction paths that are not terminated with a load, resulting in signal reflections that can require an extended settling time and consequently a reduced system clock rate. To provide for a memory solution that bridges the performance gap between DRAM and HDD, a memory subsystem is required that overcomes the speed limitations of a conventional system having a shared memory bus and stubs.